Quartus II University Interface Program
The Quartus® II University Interface Program (QUIP)
toolkit provides documentation, tutorials, data files, and sample code
to enable access to the Quartus II CAD suite at different stages
of the CAD flow. With Quartus II software and the information provided
in this kit, CAD tool developers can integrate their CAD tools and
ideas into a complete FPGA CAD flow, from register transfer level (RTL)
(as well as higher-level) descriptions of circuits to programming files
for FPGAs.
Download the QUIP toolkit
About the QUIP Toolkit
What Is the QUIP Toolkit?
The QUIP toolkit is designed to enable university (or other) researchers to plug new CAD tools and ideas into the Altera®
Quartus II software CAD flow. QUIP describes Altera's devices,
interfaces by which data can be sent into the Quartus II software at
various points in the CAD flow, and data formats in which data can be
dumped out of the Quartus II software.
This toolkit enables researchers to write point CAD tools that
perform one CAD optimization in a new or better way, and integrate
their new CAD tool into a complete CAD flow so they can get realistic
results on how this new idea improves circuit timing, routability,
device utilization, compile time, or other metrics.
Some CAD flows you could build with QUIP include:
- Replace the Quartus II hardware description language (HDL) elaboration with your own HDL elaboration.
You take in the HDL, and output gates. These gates can then be fed into
Quartus II software so it can complete the CAD flow—logic optimization,
technology mapping, placement, routing, and timing analysis. You can
then measure if you converted the HDL to gates in a way that led to
better timing or reduced device utilization.
- Replace the Quartus II technology mapping algorithm with a new one.
You use Quartus II software to map any supported input format (VHDL,
Verilog, schematics, etc.) into device primitives like logic cells.
Your tool would read in the mapped netlist output from Quartus II
software, re-optimize the logic, and re-technology map it into the
circuit elements that exist in Altera chips—logic cells, RAMs, DSP
blocks, etc. You would then feed your technology-mapped netlist back
into Quartus II software to complete the placement, routing, and
timing analysis of the circuit. You can even technology-map parts of
the circuit, and leave other parts as gates for Quartus II software to
technology-map, so you can test special-purpose technology mappers that
only work well for certain structures, or only understand some of the
Altera device features.
- Replace Quartus II software’s placement algorithm with your own.
Your input is the technology-mapped netlist from Quartus II software,
and your output is a placement to go back into Quartus II software. You
can even output partial placements—place the parts of the circuit that
your CAD tool understands (e.g., logic cells and I/O pins) and leave
complex features (e.g., RAM and DSP blocks) for Quartus II software to
place.
- Add a floorplanner to the CAD flow. You send a floorplan
into Quartus II software as a set of constraints on Quartus II
software’s placement algorithm and determine whether you can obtain
better results than when performed without your constraints.
- Add a global router to the CAD flow. You read the
technology-mapped netlist and placement from Quartus II software,
create a set of routing constraints enforcing which channels should be
used to route each signal, and send these constraints back into Quartus
II software for detailed routing.
- Perform physical synthesis. Let Quartus II software
completely implement a circuit, including placement and routing. Based
on the placement and the achieved delays in this implementation,
re-synthesize timing critical parts of the circuit to increase the
circuit speed, and feed this modified circuit netlist back into Quartus
II software. You may choose to pass placement constraints back into
Quartus II software to try to keep the placement as similar as possible
to the previous placement, or you may let Quartus II software
completely re-place the circuit.
- Develop an engineering change order (ECO) flow. Given an
implementation of a circuit by Quartus II software and a set of user
modifications to the HDL of the design, develop a method to modify the
netlist, placement, and routing of Quartus II software so that the
required changes are made as quickly and with as little disturbance of
the rest of the circuit as possible.
To see some of these CAD flows in action, go through the QUIP tutorial in tutorials/quip_tutorial/quip_tutorial.pdf after installing the kit.
This is only a partial list; many other CAD flows are possible. If
you have an interesting idea for a new CAD algorithm or flow, we may be
interested in supporting your research. For more information, contact quip@altera.com with the details of what you're planning.
QUIP Toolkit Advantages
Some of the advantages of using QUIP to evaluate new CAD ideas
instead of the usual alternative of using a CAD flow based entirely
on academic tools (e.g., SIS + RASP + VPR) are:
- You plug into a complete flow that enables you to run benchmark
circuits written in various hardware description languages (VHDL,
Verilog, AHDL), or captured in schematics, or even written in
higher-level formats like Simulink and Matlab (via Altera's DSP Builder
tool). Since most circuits today are written in hardware description
languages, this powerful front-end lets you run more real benchmarks
than you can with current purely academic CAD flows.
- You get industrial-strength timing analysis, so delay comparisons
are high-quality. Since the Quartus II software timing analyzer is
full-featured, you can evaluate the speed of circuits in many ways:
clock speed, setup time from input pins (Tsu), clock-to-out time on
output pins (Tco), and so on.
- You can also test your new CAD algorithms against those in Quartus
II software to see if you can outperform our state-of-the-art
industrial tool. (If you can, we would certainly be interested in
hearing about your results.)
- You can get real programming files for real devices, so you can test new circuit techniques in hardware if you wish.
- Since we are releasing all the details of our devices, you can
investigate CAD algorithms for the more complex features in modern
FPGAs that are usually abstracted in academic CAD flows. On the other
hand, if these complex features are not of interest to you, you can
ignore them to get a simpler CAD flow going that will still work for
simpler benchmark circuits.
- Since Quartus II software includes simulation support, you can test
that any new synthesis algorithms you develop in fact produce correct
circuits by simulating the circuits with your algorithm on and off and
checking that the output is the same.
- Quartus II software includes many visualization features that are useful in debugging and optimizing CAD tools.
Contact Altera for More Information
If you have a question or problem that is not answered by the
information provided here, or you have suggestions that would improve
future versions of the QUIP toolkit, contact the QUIP support team at quip@altera.com.
Additionally, if you are working on a research project that could be
of interest to Altera, let us know; your research project may qualify
for Altera’s financial support.
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