Altera Tutorials and Lab Exercises
A set of ready-to-teach lab exercises and tutorials have been
created for use with Altera's new Development and Education (DE2)
board. These exercises are intended for use in a first course on
digital logic design, which is included as part of the curriculum in
most computer engineering, electrical engineering, and computer science
programs. Circuits are designed for implementation on the DE2 board by
using Altera's state-of-the-art Quartus® II CAD system, which is provided at no charge for educational use.
Some of the tutorials and lab exercises refer to files found on the Altera® DE2 System CD. You can download the latest contents of the CD from the DE2 information page.
Altera provides intellectual property (IP) cores for all peripheral
devices on the DE2 board. These IP cores can be used to
create interesting and instructive undergraduate exercises and projects.
Introductory Digital Logic
Altera provides a sample curriculum showing
how you can use the DE2/DE1 boards in an introductory course on digital
logic. This curriculum provides a suggested set of lecture topics and
shows how these lectures can be aligned with the Quartus II tutorials
and DE2/DE1 lab exercises. The curriculum refers to
an example of a textbook that covers the suggested lecture
topics, but other textbooks are equally suitable.
Tutorials
Updated August 8, 2007
For digital logic courses, a set of step-by-step tutorials (see
Table 1) introduce the DE2 board and its accompanying software tools,
including various aspects of the Quartus II software.
Different versions of the tutorials are provided, in which the
illustrative circuit designs are given in either Verilog HDL, VHDL, or
Schematic Entry. Instructors should select from these versions
according to their preference.
| Table 1. Digital Logic Tutorials |
| Description |
Verilog |
VHDL |
Schematic |
| Getting Started with the DE2/DE1 Boards |
DE2, DE1 |
| Introduction to the Quartus II Software |
PDF |
PDF |
PDF |
| Using the Library of Parameterized Modules (LPM) |
PDF |
PDF |
N/A |
| Timing Considerations |
PDF |
PDF |
N/A |
|
Quartus II Simulation
|
PDF
|
PDF
|
N/A
|
| Signal Tap® II |
PDF |
PDF |
N/A |
Laboratory Exercises
Updated August 8, 2007
Altera provides a number of ready-to-teach laboratory exercises
for digital logic courses (see Table 2). A separate version of each
exercise is provided using examples in Verilog HDL and VHDL.
The ten exercises begin with fundamental concepts and show simple
operations on the DE2/DE1 boards, such as using switches and
controlling LEDs and seven-segment displays. These exercises assume
that students are just beginning to learn about digital logic concepts
and require solutions that use simple logic expressions. Subsequent
exercises progress to more advanced topics such as arithmetic circuits,
flipflops, counters, state machines, memory devices, datapaths, and
simple processors. Course instructors can adopt the entire
sequence of exercises, selected exercises, or portions of selected
exercises. Altera developed the material to be as modular as
possible so that instructors can combine the exercises with their own
teaching material.
Each exercise consists of multiple parts. In most cases, you can
reuse the solution required for the early parts in a modular fashion
for later parts. The solutions produced for early exercises are often
reusable for parts of more advanced exercises. Altera's basic approach
is to encourage students to develop their circuits in small increments
and to build larger circuits in a modular, hierarchical fashion.
| Table 2. Digital Logic Lab Exercises |
| Description |
Verilog |
VHDL |
| Lab 1: Switches, Lights, and Multiplexers |
DE2, DE1 |
DE2, DE1 |
| Lab 2: Numbers and Displays |
DE2, DE1 |
DE2, DE1 |
| Lab 3: Latches, Flipflops, and Registers |
DE2, DE1 |
DE2, DE1 |
| Lab 4: Counters |
DE2, DE1 |
DE2, DE1 |
| Lab 5: Clocks and Timers |
DE2, DE1 |
DE2, DE1 |
| Lab 6: Adders, Subtractors, and Multipliers |
DE2, DE1 |
DE2, DE1 |
| Lab 7: Finite State Machines |
DE2, DE1 |
DE2, DE1 |
| Lab 8: Memory Blocks |
DE2, DE1 |
DE2, DE1 |
| Lab 9: A Simple Processor |
DE2, DE1 |
DE2, DE1 |
| Lab 10: An Enhanced Processor |
DE2, DE1 |
DE2, DE1 |
As an aid for instructors, the complete solution for each lab
exercise is available in Verilog HDL and VHDL. Unformatted text
versions of these exercises and the source files for the figures
are also available. Click a link below to request access to the
solutions in one of the HDL languages and provide information about
your course in the body of the email.
Note: Solutions are provided only to professors or
lecturers teaching a course at a university equipped with DE2/DE1
boards. Please describe how you are using the DE2/DE1 boards in your
course(s) when submitting your request for the solutions material.
Computer Organization
Altera provides tutorials, the Altera Debug Client, and lab exercises for use in computer organization courses.
Tutorials
Updated August 8, 2007
For computer organization courses, a set of tutorials (see Table
3) explain how you can use the DE2 board with Altera's
software tools.
| Table 3. Computer Organization Tutorials |
| Description |
Verilog |
VHDL |
| Introduction to the Altera Nios® II Soft Processor |
PDF |
| Introduction to the SOPC Builder |
PDF |
PDF |
| Using the SDRAM Memory on Altera's DE2 Board |
PDF |
PDF |
Altera Monitor Program
Updated December 3, 2007
The Altera Monitor Program (see Table 4) allows students to easily
compile and debug both assembly language and C programs. It displays
the status of the Nios II processor as programs are executed, such
as the contents of processor registers and system memory, and includes
features such as program single step, breakpoints, and program trace.
| Table 4. Altera Monitor Program |
| Description |
Media |
| Tutorial |
PDF |
| Install Package |
EXE |
Laboratory Exercises
Updated August 8, 2007
Altera provides a number of ready-to-teach laboratory exercises
for computer organization courses (see Table 5). The exercises
shown below address the basic concepts of computer organization,
which include assembly language programming, subroutines, stacks,
input/output techniques, bus structure, and arbitration.
Further exercises will be available in Q1 2008.
| Table 5. Computer Organization Lab Exercises |
| Description |
Handouts |
Extra Materials |
| Lab 1: A Simple Computer System |
DE2, DE1 |
N/A |
| Lab 2: Program-Controlled Input/Output |
DE2, DE1 |
N/A |
| Lab 3: Subroutines and Stacks |
DE2, DE1 |
N/A |
| Lab 4: Polling and Interrupts |
DE2, DE1 |
N/A |
| Lab 5: Bus Communication |
DE2, DE1
|
DE2, DE1
|
| Lab 6: Bus Control and Arbitration |
DE2, DE1
|
DE2, DE1
|
| Lab 7: DMA Data Transfer |
DE2, DE1 |
N/A |
As an aid for instructors, the complete solution for each lab
exercise is available in Verilog HDL and VHDL, as well as the
appropriate Nios II assembly language or C source code.
Unformatted text versions of these exercises and the source files
for the figures are also available. Click a link below to request
access to the solutions in one of the HDL languages and provide
information about your course in the body of the email.
Note: Solutions are provided only
to professors or lecturers teaching a course at a university
equipped with DE2/DE1 boards. Please describe how you are using the
DE2/DE1 boards in your course(s) when submitting your request for the
solutions material.
|
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