IP Cores for Education
In electronic design and electronic design automation, an
intellectual property (IP) block—or IP core—is a unit of reusable
design, the use of which has been licensed to a third party. The term
is derived from the licensing of the intellectual property rights, such
as patents and copyrights, that subsist in the design.
IP cores are for hardware design what libraries are for
computer programming. They are typically used much in the style
and manner of a discrete integrated circuit on a PCB, where the
"circuit board" is a larger ASIC or FPGA design. An IP core commonly
takes the form of a computer program written in some HDL—such as
Verilog, VHDL, or SystemC—but it can also be a netlist or physical
layout, especially in analog electronics.
Altera provides a library of SOPC Builder components (IP cores),
which are listed in the table below, for all I/O devices on the DE1 and
DE2 boards. You can use these components as part of the SOPC Builder
tool in the Quartus® II software. They allow you to easily create Nios® II
systems that can access the I/O devices on the DE1 and DE2
boards. Also provided are the associated software drivers
that you can incorporate into an Altera® Debug Client
project (or an Altera Nios II IDE project). You can install the
components in the library using the installer found in the table or
download individual IP cores independently. If the IP cores are
downloaded independently, you must place them in your project directory
or in the sopc_builder\components within the Quartus II install path.
Note: The University Program IP cores are still under
development. Several of the cores are available in beta release
version. The beta release is supported directly by the Altera Debug
Client.
| Table 1. University Program IP Cores |
| IP Cores |
Description |
PDF |
ZIP |
Development Board Supported |
| Embedded Processors |
| Nios II |
Altera's embedded soft processor
|
Nios II |
DE1, DE2 |
| IP Core Bundle |
| Installer |
Installs all the available IP cores. The IP cores are listed below. |
EXE |
DE1, DE2 |
| Release Notes |
Description of releases to date |
TXT |
| Memory Controller |
| SRAM |
Provides read/write access to the SRAM chip |
PDF |
ZIP |
DE1, DE2 |
| SDRAM |
Provides read/write access to the SDRAM chip and also refreshes the chip automatically |
PDF |
ZIP |
DE1, DE2 |
| FLASH |
Not available |
PDF |
ZIP |
DE1, DE2 |
| SD Card |
Not available |
PDF |
ZIP |
DE1, DE2 |
| Communication |
| RS232 UART |
Provides a UART over the RS232 port |
PDF |
ZIP |
DE1, DE2 |
| JTAG UART |
Provides a UART over the JTAG |
PDF |
DE1, DE2 |
| Ethernet |
Not available |
PDF |
ZIP |
DE2 |
| IrDA |
Provides a UART over the IrDA port |
PDF |
ZIP |
DE2 |
| USB |
Not available |
PDF |
ZIP |
DE2 |
| Audio/Video |
| Audio/Video Configuration |
Automatically configures the audio and video chip |
PDF |
ZIP |
DE1, DE2 |
| Audio In/Out |
Provides two FIFOs for audio data |
PDF |
ZIP |
DE1, DE2 |
| Video Out |
Creates timing information for VGA display and has frame buffers for storing picture information |
PDF |
ZIP |
DE1, DE2 |
| Video In |
Not available |
PDF |
ZIP |
DE2 |
| Input/Output |
| Parallel Port |
A generic parallel input/output interface |
PDF |
ZIP |
DE1, DE2 |
| PS/2 Port |
Serial connection for the PS/2 port |
PDF |
ZIP |
DE1, DE2 |
| 16x2 LCD Character Display |
Connection to the LCD character display |
PDF |
ZIP |
DE2 |
| Avalon® to External Bus Bridge |
A bus-like interface for a slave device |
PDF |
ZIP |
DE1, DE2 |
| External Bus to Avalon Bridge |
A bus-like interface for a master device |
PDF |
ZIP |
DE1, DE2 |
The above IP cores have been developed to support Altera's
University Program and its DE1 and DE2 development and education
boards. It is important to note that Altera provides a wide range
of IP cores to implement industry-standard designs (such as a USB
controller or echo cancellation circuitry) and speed system
engineering. Altera IP cores are designed to take advantage of the
unique features of FPGAs.
Altera offers IP megafunctions for the following technology types:
View the full listing of available IP cores at the Altera IP MegaStore™.
Commercial IP Core Requests
The Altera University Program provides Altera-developed IP at no
charge to qualified research projects at universities. Please contact university@altera.com for more information.
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